1. TECHNICAL FIELD
The present invention relates to a semiconductor wafer and a semiconductor device, and a method for manufacturing thereof.
2. RELATED ART
Typical conventional semiconductor devices include, for example, a semiconductor device described in Japanese Patent Laid-Open No. 2000-214,228. A semiconductor device described in Japanese Patent Laid-Open No. 2000-214,228 is provided with an evaluation transistor, which is an object for an evaluation in electrical characteristics. Evaluation pads are coupled to a source terminal, a drain terminal and a gate terminal of evaluation transistor, respectively. These evaluation pads are formed on a surface of an interlayer insulating film, or in other words, formed on a top layer of the interconnect layer. In addition to above, prior art related to the present invention also includes a semiconductor device described in Japanese Patent Laid-Open No. 2000-260,833, in addition to a semiconductor device described in Japanese Patent Laid-Open No. 2000-214,228.
Meanwhile, concerning the characteristic evaluation device such as the above-described evaluation transistor, a plurality of characteristic evaluation devices are provided in one semiconductor device. Accordingly, a plurality of evaluation pads are also provided. However, such evaluation pad requires relatively larger area. Therefore, an increase of number of the evaluation pads leads to an increase of the chip area. Therefore, there is a room for improvement in the semiconductor device described in Japanese Patent Laid-Open No. 2000-214,228 in terms of reducing the chip area.